A Digital Architecture Employing Stochasticism for the Simulation of Hopfield Neural Nets

Abstruct -A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described. This stochastic architecture provides mussiw paruf/e/ism (since stochastic logic is very space efficient), reprogrammability (since synaptic weights are stored in digital shift registers), large dynumic runge (by using either fixed or floating-point weights), unneuling (by coupling variable neuron gains with noise from stochastic arithmetic), high execution speecLF ( = N.108 connections per second), expMdability (by cascading of multiple chips to host large networks), and practiculity (by building with very conservative MOS device technologies). Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing.